Consumers continue to demand faster computers. In computing, memory latency is the time (the latency) between initiating a request for a byte or word in memory until it is retrieved by a processor. If the data are not in the processor's cache, it takes longer to obtain them, as the processor will have to communicate with the external memory cells. Latency is therefore a fundamental measure of the speed of memory: the less the latency, the faster the reading operation.
In some conventional processors, data read from the Level-1 data cache (L1) in response to a load instruction has a latency of at least 5 cycles. Additionally, the load instruction can only be executed after the address is calculated. The latency of address calculation depends on the resolution of prior dependencies. The resolution of prior dependencies can often take 10 seconds or more to complete.
Reducing memory read latency is an open challenge.